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HT82K68E-L/HT82K68A-L Multimedia Keyboard Encoder 8-Bit MCU
Technical Document
* Tools Information * FAQs
Features
* Operating voltage: 1.8V~5.5V * 34 bidirectional I/O line and 3 CMOS output * One 8-bit programmable timer counter with overflow * HALT function and wake-up feature reduce power
consumption
* Six-level subroutine nesting * Bit manipulation instructions * 16-bit table read instructions * 63 powerful instructions * All instructions in 1 or 2 machine cycles * 20/28-pin SOP, 32-pin QFN and
interrupts
* Crystal or RC oscillator * Watchdog Timer * 3K16 program EPROM * 1608 data RAM * One external interrupt pin (shared with PC2) * 2.0V LVR by option (default disable)
48-pin SSOP packages
General Description
This device is an 8-bit high performance peripheral interface IC, designed for multiple I/O products and multimedia applications. It supports interface to a low speed PC with multimedia keyboard or wireless keyboard in Windows 95, Windows 98 or Windows 2000 environment. A HALT feature is included to reduce power consumption. The mask version HT82K68A-L is fully pin and functionally compatible with the OTP version HT82K68E-L device.
Rev. 1.30
1
August 5, 2009
HT82K68E-L/HT82K68A-L
Block Diagram
STACK0 STACK1 STACK2 STACK3 P ro g ra m ROM P ro g ra m C o u n te r STACK4 STACK5 PC2 In te rru p t C ir c u it IN T C TM R TM RC
S Y S C L K /4
8 b it S Y S C L K /4
In s tr u c tio n R e g is te r
MP0 MP1 M
U X
DATA M e m o ry
W DTS W D T P r e s c a le r W DT M
U X
RC In s tr u c tio n D ecoder ALU T im in g G e n e ra to r S h ifte r MUX PEC PE STATUS PDC PD PCC PC OSC2 OS RE VD VS S C1 SET D ACC PBC PB PAC PA PORT A PORT B PORT C PORT D PORT E PE0~PE4
OSC
PD0~PD7
PC0~PC7
PB0~PB7
PA0~PA7
Rev. 1.30
2
August 5, 2009
HT82K68E-L/HT82K68A-L
Pin Assignment
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
32 31 30 29282726 25 1 2 3 4 5 6 7 8 9 1011 1213 1415 16
PB5
24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
PB6 PB7 PA4 PA5 PA6 PA7 NC NC NC NC OSC2 OSC1 VDD RESET P E 4 (L E D ) PD3 PD2 PD1 PD0 PC7 PC6 PC5 PC4 PC3
PD0 PD1 PD2 RES VDD OSC1 OSC2 PA7
H T 8 2 K 6 8 E -L H T 8 2 K 6 8 A -L 3 2 Q F N -B
VSS PD4 PD5 PB0 PB1 PB2 PB3 PA0
PB4 PA3 PA2 PA1 PA0 PB3 PB2 PB1 PB0 PB5 PB4 PA3 PA2 4 5 6 7 8 9 10 11 12 13 14 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PB6 PB7 PA4 PA5 PA6 PA7 OSC2 OSC1 VDD RESET PC7 PC6 PC5 PC4 NC NC PD7 PD6 PD5 PD4 VSS P E 2 (L E D ) P E 3 (L E D ) PC0 PC1 PC2 PE0 PE1
PA1 PA2 PA3 PB4 PB5 PA4 PA5 PA6 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA4 PA5 PA6 PA7 OSC2 OSC1 VDD RESET PC3 PC2
PA3 PA2 PA1 PA0 PB1 PB0 VSS PE2 PC0 PC1
PA1 PA0 PB3 PB2 PB1 PB0 VSS PC1 PC2 PC3
H T 8 2 K 6 8 E -L /H T 8 2 K 6 8 A -L 2 0 S O P -A
H T 8 2 K 6 8 E -L /H T 8 2 K 6 8 A -L 2 8 S O P -A
H T 8 2 K 6 8 E -L /H T 8 2 K 6 8 A -L 4 8 S S O P -A
Pin Description
Pin Name I/O Mask Option Wake-up Pull-high or None Pull-high or None Wake-up Pull-high or None Wake-up Pull-high or None Wake-up Pull-high or None Pull-high or None Pull-high or None Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by mask option. Software* instructions determine the CMOS output or Schmitt Trigger input with or without 12K pull-high resistor. Bidirectional 8-bit input/output port. Software* instructions determine the output or Schmitt Trigger input with or without pull-high resistor. This pin is an I/O port. NMOS open drain output with pull-high resistor and can be used as DATA or CLOCK line of PS2. This pin can be configured as a wake-up input by mask option. This pin is an I/O port. NMOS open drain output with pull-high resistor and can be used as DATA or CLOCK line of PS2. This pin can be configured as a wake-up input by mask option. Bidirectional 2-bit input/output port. Each bit can be configured as a wake-up input by mask option. Software* instructions determine the CMOS output or Schmitt Trigger input with or without pull-high resistor. PC2 also as external interrupt input pin. PE0 determine whether rising edge or falling edge of PC2 to trigger the INT circuit. Bidirectional 4-bit input/output port. Software* instructions determine the CMOS output or Schmitt Trigger input with or without pull-high resistor. Bidirectional 8-bit input/output port. Software* instructions determine the CMOS output or Schmitt Trigger input with or without pull-high resistor.
PA0~PA7
I/O
PB0~PB7
I/O
PC0
I/O
PC1
I/O
PC2~PC3
I/O
PC4~PC7 PD0~PD7
I/O I/O
Rev. 1.30
3
August 5, 2009
HT82K68E-L/HT82K68A-L
Pin Name I/O Mask Option Pull-high or None Description Bidirectional input/output port. Software* instruction determine the CMOS output or Schmitt Trigger input with or without pull-high resistor. If PE0 output 1, rising edge of PC2 trigger INT circuit. PE0 output 0, falling edge of PC2 trigger INT circuit. This pin is a CMOS output structure. The pad can function as LED (SCR) drivers for the keyboard. IOL=18mA at VOL=3.4V This pin is a CMOS output structure. The pad can function as LED (NUM) drivers for the keyboard. IOL=18mA at VOL=3.4V This pin is a CMOS output structure. The pad can function as LED (CAP) drivers for the keyboard. IOL=18mA at VOL=3.4V 3/4 3/4 3/4 Crystal or RC Positive power supply Negative power supply, ground Chip reset input. Active low. Built-in power-on reset circuit to reset the entire chip. Chip can also be externally reset via RESET pin OSC1, OSC2 are connected to an RC network or a crystal for the internal system clock. In the case of RC operation, OSC2 is the output terminal for the 1/4 system clock; A 110kW resistor is connected to OSC1 to generate a 2 MHZ frequency.
PE0~PE1
I/O
PE2 PE3 PE4 VDD VSS RESET OSC1 OSC2 Note:
O O O 3/4 3/4 I I O
*: Software means the HT-IDE (Holtek Integrated Development Environment) can be configured by mask option.
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+6.0V Input Voltage .............................VSS-0.3V to VDD+0.3V Storage Temperature ...........................-50C to 125C Operating Temperature ..........................-25C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD1 Parameter Operating Voltage Operating Current (Crystal OSC) 5V IDD2 3V Operating Current (RC OSC) 5V ISTB1 3V Standby Current (WDT enabled) 5V ISTB2 3V Standby Current (WDT Disabled) 5V VIL1 Input Low Voltage for I/O Ports (Schmitt) Input High Voltage for I/O Ports (Schmitt) 3V 5V 3V 5V 3/4 3/4 3/4 3/4 No load, system HALT No load, system HALT No load, fSYS= 6MHz Test Conditions VDD 3/4 3V Conditions 3/4 No load, fSYS= 6MHz Min. 1.8 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0 0.7VDD 0.7VDD Typ. 3/4 0.7 2 0.5 2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max. 5.5 1.5 5 1.5 5 8 15 3 6 0.3VDD 0.3VDD VDD VDD
Ta=25C Unit V mA mA mA mA mA mA mA mA V V V V
VIH1
Rev. 1.30
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HT82K68E-L/HT82K68A-L
Symbol Parameter Test Conditions VDD 3V Input Low Voltage (RESET) 5V VIH2 VLVR IOL IOH ILED tPOR RPH 3V Input High Voltage (RESET) 5V Low Voltage Reset I/O Port Sink Current of PA, PB, PC, PD, PE0~1 I/O Port Source Current of PA, PB, PC, PD, PE0~4 LED Sink Current (SCR, NUM, CAP) Power-on Reset Time Internal Pull-high Resistance of PA, PB, PC, PD, PE Port 3/4 5V 5V 5V 5V 3V 5V Conditions 3/4 3/4 3/4 3/4 3/4 VOL= 0.1VDD VOH= 0.9VDD VOL=3.4V R=100kW, C=0.1mF 3/4 3/4 3/4 3/4 Crystal RC Min. 0 0 0.9VDD 0.9VDD 3/4 2 -2.5 10 50 30 15 4 2 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 2.0 4 -4 17 100 60 30 9 4.7 3/4 3/4 Max. 0.7 1.3 VDD VDD 3/4 3/4 3/4 25 150 90 45 15 8 1 20 Unit V V V V V mA mA mA ms kW kW kW kW % %
VIL2
RPH1 Df/f Df/f1
Internal Pull-high Resistance of DATA, 3V CLK 5V Frequency Variation Frequency Variation 5V 5V
A.C. Characteristics
Symbol Parameter Test Conditions VDD 1.8V System Clock (Crystal OSC) 5V fSYS2 3V System Clock (RC OSC) 5V tWDTOSC 3V Watchdog Oscillator Period 5V tWDT1 tWDT2 tRES tSST tINT Note: 3V Watchdog Time-out Period (RC) 5V Watchdog Time-out Period (System Clock) External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width tSYS= 1/fSYS1 or 1/fSYS2 3/4 3/4 3/4 3/4 Conditions 3/4 3/4 3/4 3/4 3/4 3/4 Without WDT prescaler Without WDT prescaler 3/4 Power-up or wake-up from HALT 3/4 Min. 450 450 450 450 45 35 12 9 3/4 1 3/4 1 Typ. 3/4 3/4 3/4 3/4 90 78 23 19 1024 3/4 1024 3/4 Max. 4000 8000 6000 8000 180 130 45 35 3/4 3/4 3/4 3/4
Ta=25C Unit kHz kHz kHz kHz ms ms ms ms tSYS ms tSYS ms
fSYS1
Rev. 1.30
5
August 5, 2009
HT82K68E-L/HT82K68A-L
Functional Description
Execution Flow The device system clock is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The 12-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a maximum of 4096 addresses. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. Once a control transfer takes place, an additional dummy cycle is required. Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized with 307216 bits, addressed by the program counter and table pointer.
T1 S y s te m C lo c k
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
O S C 2 ( R C o n ly ) ( N M O S o p e n d r a in o u tp u t) PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow
Mode Initial reset External interrupt Timer counter overflow Skip Loading PCL Jump, call branch Return from subroutine
Program Counter *11 0 0 0 *11 #11 S11 *10 0 0 0 *10 #10 S10 *9 0 0 0 *9 #9 S9 *8 0 0 0 *8 #8 S8 *7 0 0 0 @7 #7 S7 *6 0 0 0 @6 #6 S6 *5 0 0 0 @5 #5 S5 *4 0 0 0 @4 #4 S4 *3 0 0 1 @3 #3 S3 *2 0 1 0 @2 #2 S2 *1 0 0 0 @1 #1 S1 *0 0 0 0 @0 #0 S0
Program Counter+2
Note: *11~*0: Program counter bits #11~#0: Instruction code bits
S11~S0: Stack register bits @7~@0: PCL bits
Rev. 1.30
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August 5, 2009
HT82K68E-L/HT82K68A-L
000H 008H D e v ic e in itia liz a tio n p r o g r a m T im e r /e v e n t c o u n te r in te r r u p t s u b r o u tin e
n00H nFFH
L o o k - u p ta b le ( 2 5 6 w o r d s )
P ro g ra m ROM
BFFH
L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 6 b its N o te : n ra n g e s fro m 0 to B
Program Memory Certain locations in the program memory are reserved for special usage:
* Location 000
Table Higher-order byte register (TBLH) is read only. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. All table related instructions need 2 cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into six levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgement, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. Data Memory - RAM The data memory is designed with 184 8 bits. It is divided into two functional groups: special function registers and general purpose data memory (1608). Most of them are read/write, but some are read only. The unused space before 60H is reserved for future expanded usage and reading these locations will get the result 00H. The general purpose data memory, addressed from 60H to FFH, is used for data and control information under instruction command. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set Table Location
This area is reserved for the initialization program. After chip reset, the program always begins execution at location 000H.
* Location 004H
Location 004H is reserved for external interrupt service program. If the PC2 (external input pin) is activated, the interrupt is enabled, and the stack is not full, the program begins execution at location 004H. The pin PE0 determine whether the rising or falling edge of the PC2 to activate external interrupt service program.
* Location 008H
This area is reserved for the timer counter interrupt service program. If timer interrupt results from a timer counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
* Table location
Any location in the ROM space can be used as look-up tables. The instructions TABRDC [m] (the current page, one page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, the remaining 1 bit is read as 0. The
Instruction(s) TABRDC [m] TABRDL [m]
*11 P11 1
*10 P10 0
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Note: *11~*0: Table location bits @7~@0: Table location bits Rev. 1.30 7
P11~P8: Current program counter bits
August 5, 2009
HT82K68E-L/HT82K68A-L
and reset by the SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible through Memory pointer registers (MP0;01H, MP1;03H).
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 20H 60H G e n e ra l P u rp o s e D a ta M e m o ry (1 6 0 B y te s ) FFH PA PAC PB PBC PC PCC PD PDC PE PEC TM R TM RC S p e c ia l P u r p o s e D a ta M e m o ry ACC PCL TBLP TBLH W DTS STATUS IN T C In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1
Accumulator The accumulator is closely related to the ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but also changes the status register. Status Register - Status The 8-bit status register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF) and watch dog time-out flag (TO). The status register not only records the status information but also controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flags. It should be noted that operations related to the status register may give different results from those intended. The TO and PDF flags can only be changed by system power up, Watchdog Timer overflow, executing the HALT instruction and clearing the Watchdog Timer. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of status are important and if the subroutine can corrupt the status register, precaution must be taken to save it properly.
:U nused. R e a d a s 0 0
RAM Mapping Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] can access the data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly will return the result 00H. Writing indirectly results in no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are 8-bit registers which can be used to access the data memory by combining corresponding indirect addressing registers.
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HT82K68E-L/HT82K68A-L
Bit No. 0 Label C Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or if no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared when either a system power-up or executing the CLR WDT instruction. PDF is set by executing a HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register Interrupt The device provides an internal timer counter interrupt and an external interrupt shared with PC2. The interrupt control register (INTC;0BH) contains the interrupt control bits to set not only the enable/disable status but also the interrupt request flags. Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupt have the wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack followed by a branch to a subroutine at the specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register and Status register (STATUS) are altered by the interrupt service Bit No. 0 1 2 3 4 5 6, 7 Label EMI EEI ET0I 3/4 EIF T0F 3/4 program which corrupt the desired control sequence, the contents should be saved in advance. The internal timer counter interrupt is initialized by setting the timer counter interrupt request flag (T0F; bit 5 of INTC), which is normally caused by a timer counter overflow. When the interrupt is enabled, and the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The external interrupt is shared with PC2. The external interrupt is activated, the related interrupt request flag (EIF; bit4 of INTC) is then set. When the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will also be cleared to disable other interrupts. The external interrupt (PC2) can be triggered by a high to low transition, or a low to high transition of the PC2, which is dependent on the output level of the PE0. When PE0 is output high, the external interrupt is triggered by a low to high transition of the PC2. When PE0 is output low, the external interrupt is triggered by a high to low transition of PC2.
1 2 3 4 5 6, 7
AC Z OV PDF TO 3/4
Function Controls the master (global) interrupt (1= enabled; 0= disabled) Control the external interrupt Controls the timer counter interrupt (1= enabled; 0= disabled) Unused bit, read as 0 External interrupt flag Internal timer counter request flag (1= active; 0= inactive) Unused bit, read as 0 INTC (0BH) Register
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HT82K68E-L/HT82K68A-L
During the execution of an interrupt subroutine, other interrupt acknowledgements are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, a RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External interrupt 1 Timer counter overflow Vector 04H 08H
V OSC1 OSC1 OSC2 C r y s ta l O s c illa to r fS Y S /4 (N M O S O p e n D r a in O u tp u t) OSC2 RC O s c illa to r
chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift needed for oscillator, no other external components are needed. Instead of a crystal, the resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works for a period of approximately 78ms. The WDT oscillator can be disabled by mask option to conserve power.
DD
Once the interrupt request flags (T0F) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is suggested that a program does not use the CALL subroutine within the interrupt subroutine. Because interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications, if only one stack is left and enabling the interrupt is not well controlled, once the CALL subroutine operates in the interrupt subroutine it will damage the original control sequence. Oscillator Configuration There are two oscillator circuits in the microcontroller. Both are designed for system clocks; the RC oscillator and the Crystal oscillator, which are determined by mask options. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and resists the external signal to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VDD is needed and the resistance must range from 20kW to 510kW. The system clock, divided by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature and the
S y s te m c lo c k /4 M ask O p tio n S e le c t
System Oscillator Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by mask options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT results in no operation. Once the internal WDT oscillator (RC oscillator normally with a period of 78ms) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with temperature, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds.
W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
W DT OSC
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
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August 5, 2009
HT82K68E-L/HT82K68A-L
If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the WDT logic can be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for user defined flags, which can be used to indicate some specified status. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 WDTS (09H) Register The WDT overflow under normal operation will initialize chip reset and set the status bit TO. An overflow in the HALT mode, initializes a warm reset only when the program counter and stack pointer are reset to zero. To clear the contents of the WDT (including the WDT prescaler ), three methods are adopted; external reset (a low level to RESET), software instruction(s), or a HALT instruction. There are two types of software instructions; CLR WDT and CLR WDT1/CLR WDT2. Of these two types of instruction, only one can be active depending on the mask option - CLR WDT times selection option. If the CLR WDT is selected (ie. CLR WDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case CLR WDT1 and CLR WDT2 are chosen (ie. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip because of the time-out. Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following...
* The system oscillator will turn off but the WDT oscillator
keeps running (if the WDT oscillator is selected).
* The contents of the on-chip RAM and registers
remain unchanged.
* WDT and WDT prescaler will be cleared and recount
again (if the WDT clock has come from the WDT oscillator). * All I/O ports maintain their original status.
* The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an external reset, interrupt, and external falling edge signal on port A and port C [0:3] or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. Examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared when system power-up or executing the CLR WDT instruction and is set when the HALT instruction is executed. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the others keep their original status. On the other hand, awakening from an external interrupt (PC2), two sequences may happen. If the interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. But if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. The port A or port C [0:3] wake-up can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. Once a wake-up event occurs, and the system clock comes from a crystal, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, the device will insert a dummy period after the wake-up. If the system clock comes from an RC oscillator, it continues operating immediately. If the wake-up results in next instruction execution, this will execute immediately after the dummy period is completed. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status.
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August 5, 2009
HT82K68E-L/HT82K68A-L
Reset There are three ways in which a reset can occur:
* RESET reset during normal operation * RESET reset during HALT * WDT time-out reset during normal operation
VDD RESET S S T T im e - o u t C h ip R eset tS
ST
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm reset that just resets the program counter and stack pointer, leaving the other circuits to remain in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 0 u 1 RESET Conditions RESET reset during power-up RESET reset during normal operation RESET wake-up HALT WDT time-out during normal operation WDT wake-up HALT
RESET H ALT W DT
Reset Timing Chart
V
DD
RESET
Reset Circuit
W DT T im e - o u t R eset
W a rm
R eset
Note: u means unchanged To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system powers up or when it awakes from the HALT state. When a system power-up occurs, the SST delay is added during the reset period. But when the reset comes from the RESET pin, the SST delay is disabled. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status is shown below. Program Counter Prescaler WDT Timer counter Input/output ports Stack Pointer 000H Clear Clear. After master reset, WDT begins counting Off Input mode Points to the top of the stack
OSC1
SST 1 0 -s ta g e R ip p le C o u n te r P o w e r - o n D e te c tio n
C o ld R e s e t
Reset Configuration Timer Counter A timer counter (TMR) is implemented in the microcontroller. The timer counter contains an 8-bit programmable count-up counter and the clock may come from the system clock divided by 4. Using the internal instruction clock, there is only one reference time-base. There are two registers related to the timer counter; TMR ([0DH]), TMRC ([0EH]). Two physical registers are mapped to TMR location; writing TMR makes the starting value be placed in the timer counter preload register and reading TMR gets the contents of the timer counter. The TMRC is a timer counter control register, which defines some options.
Bit No. 0~3 4 5 6 7
Label 3/4 TON 3/4 TM0 TM1 Unused bit, read as "0"
Function
To enable/disable timer counting (0= disabled; 1= enabled) Unused bit, read as "0" 10= Timer mode (internal clock) TMRC (0EH) Register
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HT82K68E-L/HT82K68A-L
The state of the registers is summarized in the following table: Register MP0 MP1 ACC Program Counter TBLP TBLH WDTS STATUS INTC TMR TMRC PA PAC PB PBC PC PCC PD PDC PE PEC Note: Reset (Power On) xxxx xxxx xxxx xxxx xxxx xxxx 000H xxxx xxxx -xxx xxxx 0000 0111 --00 xxxx -000 0000 xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 * stands for warm reset u stands for unchanged x stands for unknown WDT Time-out RESET Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --1u uuuu -000 0000 0000 0000 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --uu uuuu -000 0000 0000 0000 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 RESET Reset (HALT) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --00 uuuu -000 0000 0000 0000 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 WDT Time-out (HALT) uuuu uuuu uuuu uuuu uuuu uuuu 000H* uuuu uuuu -uuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu ---u uuuu
S y s te m
C lo c k /4
D a ta B u s TM 1 TM 0 T im e r C o u n te r P r e lo a d R e g is te r R e lo a d
TM 1 TM 0 TON
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
T im e r C o u n te r
O v e r flo w to In te rru p t
Timer Counter
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HT82K68E-L/HT82K68A-L
In the timer mode, once the timer counter starts counting, it will count from the current contents in the timer counter to FFH. Once overflow occurs, the counter is reloaded from the timer counter preload register and generates the interrupt request flag (TF; bit 5 of INTC) at the same time. To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC) should be set to 1. In the case of timer counter OFF condition, writing data to the timer counter preload register will also reload that data to the timer counter. But if the timer counter is turned on, data written to it will only be kept in the timer counter preload register. The timer counter will still operate until overflow occurs. When the timer counter (reading TMR) is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the programmer. Input/Output Ports There are 34 bidirectional input/output lines in the microcontroller, labeled from PA to PE, which are mapped to the data memory of [12H], [14H], [16H], [18H] and [1AH] respectively. All these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H, 18H or 1AH). For output operation, all data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC, PEC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor (mask option) structures can be reconfigured dynamically (i.e., on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write 1. The pull-high resistance will exhibit automatically if the pull-high option is selected. The input source(s) also depend(s) on the control register. If the control register bit is 1, input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H, 19H and 1BH. After a chip reset, these input/output lines stay at high levels or floating (mask option). Each bit of these input/output latches can be set or cleared by the SET [m].i or CLR [m].i (m=12H, 14H, 16H, 18H or 1AH) instruction. Some instructions first input data and then follow the output operations. For example, the SET [m].i, CLR [m].i, CPL [m] and CPLA [m] instructions read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A and port C [0:3] has the capability to wake-up the device. PC2 is shared with the external interrupt pin, PE2~PE4 is defined as CMOS output pins only. PE0 can determine whether the high to low transition, or the low to high transition of PC2 to activate the external subroutine, when PE0 output high, the low to high transition of PC2 to trigger the external subroutine, when PE0 output low, the high to low transition of PC2 to trigger the external subroutine. PE2~PE4 is configured as CMOS output only and is used to drive the LED. PC0, PC1 is configured as NMOS open drain output with 4.6kW pull-high resistor such that it can easy to use as DATA or CLOCK line of PS2 keyboard application.
V D a ta B u s D CK S Q V W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D W r ite I/O CK S Q M R e a d I/O S y s te m W a k e -u p ( P A & P C 0 ~ P C 3 o n ly ) U X Q Q
DD
DD
W eak P u ll- u p M a s k O p tio n PA0 PB0 PC0 PD0 PE0 ~PA ~PB ~PC ~PD ~PE 4 7 7 7 7
M a s k O p tio n
Input/Output Ports
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HT82K68E-L/HT82K68A-L
Low Voltage Reset - LVR The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
V 2 .0 V 2 .0 V
* The low voltage (0.9V~VLVR) has to remain in their
The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
5 .5 V
LVR
original state to exceed 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function.
* The LVR uses the OR function with the external
0 .9 V
RES signal to perform chip reset. The relationship between VDD and VLVR is shown below.
Note:
VOPR is the voltage range for proper chip operation at 4MHz system clock.
V 5 .5 V
DD
V
LVR
LVR
D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the reset mode.
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HT82K68E-L/HT82K68A-L
ROM Code Option The following shows six kinds of ROM code option in the device. All the ROM code options must be defined to ensure proper system function. No. 1 ROM Code Option OSC type selection. This option is to decide if an RC or Crystal oscillator is chosen as system clock. If the Crystal oscillator is selected, the XST (Crystal Start-up Timer) default is activated, otherwise the XST is disabled. WDT source selection. There are three types of selection: on-chip RC oscillator, instruction clock or disable the WDT. CLRWDT times selection. This option defines the way to clear the WDT by instruction. One time means that the CLR WDT instruction can clear the WDT. Two times means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, only then will the WDT be cleared. Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA and PC [0:3] only) all have the capability to wake-up the chip from a HALT. Pull-high selection. This option is to decide whether the pull-high resistance is visible or not in the input mode of the I/O ports. Each bit of an I/O port can be independently selected. LVR enable/disable. User can configure whether enable or disable the circuit by configuration option. The Input type only Schmitt Trigger input type can used for HT82K68E-L. The Input type Schmitt Trigger input or inverter input type can used for HT82K68A-L.
2
3
4 5 6 7
Application Circuits
RC Oscillator for Multiple I/O Applications Crystal Oscillator or Ceramic Resonator for Multiple I/O Applications
F .B . 10mF R e s e rv e fo r R e s o n a to r
V
DD
F .B . 10m. V 40kW fS Y S /4 (N M O S O p e n D r a in O u tp u t) V
0 .1 m F
VDD
V PA PA PA PA PA PA PA PA PB PB PB PB PB PB PB PB PD PD PD PD PD PD PD PD PC PC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 6 7 C0 C1 C2 C3 C4 C5 C6 C7 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17
DD
0 .1 m F
VDD
DD
OSC1
OSC1 OSC2
DD
OSC2 V
DD
IN 4 1 4 8
47kW RESET 0 .1 m F V
DD
IN 4 1 4 8
47kW RESET 0 .1 m F V
DD
CAP NUM SCR CLK DATA CLK DATA
CAP NUM SCR CLK DATA CLK DATA
PA PA PA PA PA PA PA PA PB PB PB PB PB PB PB PB PD PD PD PD PD PD PD PD PC PC
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
C0 C1 C2 C3 C4 C5 C6 C7 R0 R1 R2 R3 R4 R5 R6 R7 0 1 2 3 4 5 6 7 6 7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17
H T 8 2 K 6 8 E -L /H T 8 2 K 6 8 A -L
H T 8 2 K 6 8 E -L /H T 8 2 K 6 8 A -L
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HT82K68E-L/HT82K68A-L
Instruction Set
Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description
Cycles
Flag Affected
Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
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HT82K68E-L/HT82K68A-L
Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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HT82K68E-L/HT82K68A-L
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z
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HT82K68E-L/HT82K68A-L
CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
Rev. 1.30
21
August 5, 2009
HT82K68E-L/HT82K68A-L
CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation Affected flag(s)
Rev. 1.30
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August 5, 2009
HT82K68E-L/HT82K68A-L
INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
Rev. 1.30
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August 5, 2009
HT82K68E-L/HT82K68A-L
OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Affected flag(s) RETI Description Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Operation Affected flag(s) RL [m] Description Operation Affected flag(s) RLA [m] Description
Operation Affected flag(s)
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HT82K68E-L/HT82K68A-L
RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation Affected flag(s) RRA [m] Description
Operation Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
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25
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HT82K68E-L/HT82K68A-L
SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
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HT82K68E-L/HT82K68A-L
SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
Rev. 1.30
27
August 5, 2009
HT82K68E-L/HT82K68A-L
SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Affected flag(s) SZ [m] Description Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation Affected flag(s) TABRDL [m] Description Operation Affected flag(s)
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HT82K68E-L/HT82K68A-L
XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
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HT82K68E-L/HT82K68A-L
Package Information
20-pin SOP (300mil) Outline Dimensions
20
A
11
B
1
C C'
10
G H
D E F
a
* MS-013
Symbol A B C C D E F G H a
Dimensions in mil Min. 393 256 12 496 3/4 3/4 4 16 8 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 512 104 3/4 12 50 13 8
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30
August 5, 2009
HT82K68E-L/HT82K68A-L
28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1
14
C C' G H D E F
a
* MS-013
Symbol A B C C D E F G H a
Dimensions in mil Min. 393 256 12 697 3/4 3/4 4 16 8 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 12 50 13 8
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HT82K68E-L/HT82K68A-L
SAW Type 32-pin (5mm5mm) QFN Outline Dimensions
D 25 b E e A1 A3 L A 17 16 24
D2 32 1 E2 8 9 K
Symbol A A1 A3 b D E e D2 E2 L K
Dimensions in inch Min. 0.028 0.000 3/4 0.007 3/4 3/4 3/4 0.049 0.049 0.012 3/4 Nom. 3/4 3/4 0.008 3/4 0.197 0.197 0.020 3/4 3/4 3/4 3/4 Max. 0.031 0.002 3/4 0.012 3/4 3/4 3/4 0.128 0.128 0.020 3/4
Symbol A A1 A3 b D E e D2 E2 L K
Dimensions in mm Min. 0.70 0.00 3/4 0.18 3/4 3/4 3/4 1.25 1.25 0.30 3/4 Nom. 3/4 3/4 0.20 3/4 5.00 5.00 0.50 3/4 3/4 3/4 3/4 Max. 0.80 0.05 3/4 0.30 3/4 3/4 3/4 3.25 3.25 0.50 3/4
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32
August 5, 2009
HT82K68E-L/HT82K68A-L
48-pin SSOP (300mil) Outline Dimensions
48 A
25 B
1 C C'
24
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 395 291 8 613 85 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 637 99 3/4 10 35 12 8
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HT82K68E-L/HT82K68A-L
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 20W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0
+0.5/-0.2
2.00.5 24.8
+0.3/-0.2
30.20.2
SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0
+0.5/-0.2
2.00.5 24.8
+0.3/-0.2
30.20.2
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SAW Type QFN 32-pin (5mm5mm) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.00.1 13.0
+0.5/-0.2
2.00.5 12.5
+0.3/-0.2
3/4
SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.00.1 13.0
+0.5/-0.2
2.00.5 32.2
+0.3/-0.2
38.20.2
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HT82K68E-L/HT82K68A-L
Carrier Tape Dimensions
D
E F W C
P0
P1
t
B0
D1
P A0
K0
R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e .
SOP 20W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Description Carrier Tape Width Dimensions in mm 24.0
+0.3/-0.1
12.00.1 1.750.10 11.50.1 1.5 1.50
+0.1/-0.0 +0.25/-0.00
4.00.1 2.00.1 10.80.1 13.30.1 3.20.1 0.300.05 21.30.1
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.10 11.50.1 1.5 1.50
+0.1/-0.0 +0.25/-0.00
4.00.1 2.00.1 10.850.10 18.340.10 2.970.10 0.350.01 21.30.1
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HT82K68E-L/HT82K68A-L
D
E F
P0
P1
t
W C
B0
D1
P K2 A0
K1
R e e l H o le ( C ir c le ) p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . R e e l H o le ( E llip s e ) IC
SSOP 48W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 32.00.3 16.00.1 1.750.10 14.20.1 2 Min. 1.50
+0.25/-0.00
4.00.1 2.00.1 12.00.1 16.20.1 2.40.1 3.20.1 0.350.05 25.50.1
Rev. 1.30
37
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HT82K68E-L/HT82K68A-L
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.30
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